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M48Z512A M48Z512AY
4 Mbit (512Kb x8) ZEROPOWER(R) SRAM
INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z512A: 4.50V VPFD 4.75V - M48Z512AY: 4.20V VPFD 4.50V BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 512K x 8 SRAMs DESCRIPTION The M48Z512A/512AY ZEROPOWER(R) RAM is a non-volatile 4,194,304 bit Static RAM organized as 524,288 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32 pin DIP Module. The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. Table 1. Signal Names
A0-A18 DQ0-DQ7 E G W VCC VSS May 1999 Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground
32 1
PMDIP32 (PM) Module
Figure 1. Logic Diagram
VCC
19 A0-A18 M48Z512A M48Z512AY
8 DQ0-DQ7
W E G
VSS
AI02043
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Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TBIAS TSLD
(2)
Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Temperature Under Bias Lead Soldering Temperature for 10 seconds Input or Output Voltages Supply Voltage
Value 0 to 70 -40 to 85 -40 to 85 260 -0.3 to 7 -0.3 to 7
Unit C C C C V V
VIO VCC
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO 4.75V to 5.5V or 4.5V to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Pin Connections
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
32 1 31 2 30 3 29 4 28 5 27 6 26 7 8 M48Z512A 25 9 M48Z512AY 24 23 10 22 11 21 12 20 13 19 14 18 15 17 16
AI02044
VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
DESCRIPTION (cont'd) The M48Z512A/512AY has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which sustains data until valid power returns. READ MODE The M48Z512A/512AY is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripplethrough access of data from eight of 4,194,304 locations in the static storage array. Thus, the unique address specified by the 19 Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be avail-
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Figure 3. Block Diagram
VCC
A0-A18
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
512K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI02045
able after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. WRITE MODE The M48Z512A/512AY is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from E or tWHAX from W prior to the initiation of another read or write cycle. Data-in must be valid tDVEH or tDVWH prior to the end of write and remain valid for tEHDX or tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
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M48Z512A, M48Z512AY
Table 5. Capacitance (1, 2) (TA = 25 C, f = 1 MHz )
Symbol CIN CIO
(3)
Parameter Input Capacitance Input / Output Capacitance
Test Condition VIN = 0V VOUT = 0V
Min
Max 10 10
Unit pF pF
Notes: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected
Table 6. DC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI ILO
(1) (1)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, Outputs open E = VIH E VCC - 0.2V
Min
Max 1 1 115 10 5
Unit A A mA mA mA V V V V
ICC ICC1 ICC2 VIL VIH VOL VOH
-0.3 2.2 IOL = 2.1mA IOH = -1mA 2.4
0.8 VCC + 0.3 0.4
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70C)
Symbol VPFD VPFD VSO tDR(2) Parameter Power-fail Deselect Voltage (M48Z512A) Power-fail Deselect Voltage (M48Z512AY) Battery Back-up Switchover Voltage Data Retention Time 10 Min 4.5 4.2 Typ 4.6 4.3 3 Max 4.75 4.5 Unit V V V YEARS
Notes: 1. All voltages referenced to VSS. 2. At 25C
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Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70C)
Symbol tF (1) tFB
(2)
Parameter VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time Write Protect Time from VCC = VPFD VSO to VPFD (max) VCC Rise Time E Recovery Time
Min 300 10 40 0 40
Max
Unit s s
tWP tR tER
150
s s
120
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
tDR
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
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Table 9. Read Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z512A / M48Z512AY Symbol Parameter Min tAVAV tAVQV
(1)
-70 Max Min 85 70 70 35 5 5 30 20 5 5 5 5
-85 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
70
ns 85 85 45 ns ns ns ns ns 35 25 ns ns ns
tELQV (1) tGLQV tELQX tGLQX
(1) (2) (2)
tEHQZ (2) tGHQZ tAXQX
(2) (1)
Notes: 1. CL = 100pF (see Figure 4). 2. CL = 5pF (see Figure 4)
Figure 6. Address Controlled, Read Mode AC Waveforms
A0-A18 tAVAV tAVQV DQ0-DQ7 DATA VALID
AI01220
tAXQX
Note: Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
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M48Z512A, M48Z512AY
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01221
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
DATA RETENTION MODE With valid VCC applied, the M48Z512A/512AY operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data.
The internal coin cell will maintain data in the M48Z512A/512AY after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external Vcc. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on Battery Storage Life refer to the Application Note AN1012
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M48Z512A, M48Z512AY
Table 10. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z512A / M48Z512AY Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ
(1,2)
-70 Max Min 85 0 0 65 75 5 15 35 35 0 10 25 65 65 5 75 75 5
-85 Max
Unit
Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition
70 0 0 55 55 5 15 30 30 0 10
ns ns ns ns ns ns ns ns ns ns ns 30 ns ns ns ns
tAVWH tAVEH tWHQX
(1,2)
Notes: 1. CL = 5pF (see Figure 4). 2. If E goes low simultaneously with W going low, the outputs remain in the high-impedance state.
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 8. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z512A, M48Z512AY
Figure 9. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01222
tWHAX
tWHQX
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01223
tELEH
tEHAX
Note: Output Enable (G) = High.
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M48Z512A, M48Z512AY
ORDERING INFORMATION SCHEME Example: M48Z512AY -85 PM 1
Supply Voltage and Write Protect Voltage 512A 512AY VCC = 4.75V to 5.5V VPFD = 4.5V to 4.75V VCC = 4.5V to 5.5V VPFD = 4.2V to 4.5V -70 -85
Speed 70ns 85ns PM
Package PMDIP32 1
Temp. Range 0 to 70C Extended Temperature
9 (1)
Note: 1. Contact Sales Offices for availability of Extended Temperature.
For a list of available options (Speed, Package, etc.) or for further information or any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M48Z512A, M48Z512AY
PMDIP32 - 32 pin Plastic DIP Module
Symb Typ A A1 B C D E e1 e3 eA L S N mm Min 9.27 0.38 0.43 0.20 42.42 18.03 2.30 34.43 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.81 42.08 16.00 3.81 2.79 Typ inches Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.355 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.656 0.630 0.150 0.110
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Drawing is not to scale.
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M48Z512A, M48Z512AY
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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